The heterogeneous multi-core platform provides flexibility for system design by integrating different types of processing cores, so that applications can dynamically select different types of processing cores according to their requirements and realize efficient operation of applications. With the development of semiconductor technology, the number of integrated cores on a single chip has increased, making the modern multi-core processors have a higher power density, and this will cause the chip temperature to rise, which will eventually cause a certain negative impact on the system performance. To make the performance advantages of heterogeneous multi-core processing system fully utilized, a dynamic mapping method was proposed to maximize the performance of heterogeneous multi-core systems under the premise of satisfying temperature safe power. In this method, two heterogeneous indices of heterogeneous multi-core systems including core type and thermal susceptibility were considered to determine the mapping scheme:the first heterogeneous index is the core type. Different types of processing cores have different characteristics, so they are suitable for processing different applications. The second heterogeneous index is thermal susceptibility. Different processing core positions on the chip have different thermal susceptibility. The processing cores closer to the center receive more heat transfer from other processing cores, so that they have higher temperature. For the above, a neural network performance predictor was created to match threads to processing core types, and the Thermal Safe Power (TSP) model was used to map the matched threads to specific locations on the chip. Experimental results show that the proposed method achieves about 53% increase of the average number of instructions executed by the program in each clock cycle-Instruction Per Cycle (IPC) under the premise of ensuring thermal safety constraints compared with the common Round Robin Scheduler (RRS).

Nowadays, with the development of semiconductor technology and the requirement of the diversification of applications, heterogeneous multi-core processors have been widely used in high-performance embedded systems. How to manage and distribute the available resources (such as processing cores) during running in order to meet the requirements in performance and power consumption of the system and the applications that the system runs is a main challenge that the system focuses. However, although some mainstream resource management techniques have achieved good results in terms of performance and/or power consumption optimization, they lack the strict reliability guarantee for the resource management component. Therefore, a method based on Discrete Controller Synthesis (DCS) was proposed to automatically and reliably design the online resource management scheme for heterogeneous multi-core systems, which applies DCS (which is formal and can construct management control components automatically) to the design of online resource management components for heterogeneous multi-core systems. In this method, the heterogeneous system’s running behaviors (such as how to distribute the processing cores to the applications) were described by using the formal models, and the online resource management problem was transformed to a DCS problem aiming at one system management objective (such as maximizing system performance). On this basis, the existing DCS tools were used to illustrate and validate the proposed method, and the scalability of the DCS method was evaluated.